This file describes design decisions around the schematic editor and its files.
Since the wiring tool requires knowlege of wires connected together in real time the in memory schematic must have information on what pin is connected to what.
There are 2 ways to handle this
| Operation | CPTR | NLSTMEM |
|---|---|---|
| Loading Schematic file | Complicated | Easy |
| Loading Netlist file | Complicated | Easy - just readthe ASCII file and load into the binary data structure in memory |
| Saveing Netlist file | Complicated- must check every part for connections avoiding ovrlaps | Easy - just write an ASCII version of the binary netlist in memory |
| DRC Checking | Must check from every component, checking for overlapped paths as we go | Can perform most checking by one pass though the memory image |
| Wire Dragging | Each wire knows about its adjacent connections so knows which wires to drag and which wires to stretch. | Each wire can check the NLSTMEM for all its connections so can determin very quickly all connected wires and pins. |
| Netlist renaming | Must be handled in separate code | Kept in the central NLSTMEM list. |
The NLSTMEM option sounds better in terms of handling files requred for the schematic editor. It provides:
Currently the CPTR option is implemented in the wiring tool and connection tool for testing but it is apparent that switiching to the NLSTMEM option is very adventagous